Job Description
Join Aetheria Systems as we architect the bridge between classical silicon and the post-silicon era. In 2026, we are not just predicting the future; we are building the infrastructure for the next 100 years of computing. We are seeking a visionary Senior Quantum Interface Architect to lead the development of high-level abstraction layers for our next-generation quantum processors.
In this role, you will define how human logic translates into qubit operations, ensuring stability, coherence, and scalability in a rapidly evolving landscape. You will work alongside physicists and semiconductor engineers to create the operating systems that will power everything from next-gen AI to secure global communications.
Why join us?
- Work on the bleeding edge of technology with a competitive equity package.
- Define the standards for 2026 and beyond.
- Flexible remote-first culture with quarterly innovation sprints.
Responsibilities
- Architect and design high-level quantum assembly languages (QAL) and compilers for our proprietary hardware.
- Develop middleware that translates classical algorithms into quantum circuits with minimal error propagation.
- Collaborate with quantum hardware teams to optimize signal coherence and reduce decoherence errors in software interfaces.
- Lead the implementation of quantum error correction protocols within the user-facing software stack.
- Mentor junior engineers and researchers in quantum software engineering best practices.
- Conduct rigorous testing of interface latency and throughput under simulated 2026 network conditions.
Qualifications
- Master’s or PhD in Computer Science, Physics, or Electrical Engineering with a focus on Quantum Information.
- 5+ years of experience in systems programming, particularly with C++, Rust, or Python.
- Deep understanding of quantum computing concepts, including superposition, entanglement, and quantum gates.
- Experience with quantum programming frameworks such as Qiskit, Cirq, or Forest.
- Proven track record of optimizing low-level code for performance and hardware constraints.
- Ability to communicate complex technical concepts to non-technical stakeholders.